?001 fairchild semiconductor corporation hplr3103, HPLU3103 rev. b hplr3103, HPLU3103 52a, 30v, 0.019 ohm, n-channel logic level, power mosfets these are n-channel enhancement mode silicon gate power ?ld effect transistors. they are advanced power mosfets designed, tested, and guaranteed to withstand a speci?d level of energy in the breakdown avalanche mode of operation. all of these power mosfets are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. features logic level gate drive 52a ? , 30v low on-resistance, r ds(on) = 0.019 ? uis rating curve related literature - tb334, ?uidelines for soldering surface mount components to pc boards ? calculated continuous current based on maximum allowable junction temperature. package limited to 20a continuous, see figure 9. symbol packaging jedec to-251aa jedec to-252aa ordering information part number package brand HPLU3103 to-251aa hp3103 hplr3103 to-252aa hp3103 note: when ordering, use the entire part number. add the suf? t to obtain the to-252aa variant in tape and reel, e.g., hplr3103t. d g s drain (flange) drain source gate drain (flange) gate source data sheet december 2001
?001 fairchild semiconductor corporation hplr3103, HPLU3103 rev. b absolute maximum ratings t c = 25 o c, unless othewise speci?d hplr3103, HPLU3103 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16v v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 52 390 a a single pulse avalanche energy (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as 240 mj power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 0.71 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v 30 - - v gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a1--v zero gate voltage drain current i dss v ds = 30v, v gs = 0v - - 25 a v ds = 24v, v gs = 0v, t c = 125 o c - - 250 a gate to source leakage current i gss v gs = 16v - - 100 na breakdown voltage temperature coefficient ? v (br)dss / ? t j reference to 25 o c, i d = 1ma - 0.037 - v drain to source on resistance (note 3) r ds(on) i d = 28a, v gs = 10v - - 0.019 ? i d = 23a, v gs = 4.5v - - 0.024 ? turn-on delay time t d(on) v dd = 15v, i d ? 34a, r l = 0.441 ? , v gs = 4.5v, r gs =3.4 ?, i g(ref) = 3ma -9 - ns rise time t r - 210 - ns turn-off delay time (note 3) t d(off) -20 - ns fall time t f -54 - ns total gate charge q g v dd = 24v i d ? 34a, v gs = 4.5v (figure 6) - - 50 nc gate to source charge q gs - - 14 nc gate to drain ?iller?charge q gd - - 28 nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 5) - 1600 - pf output capacitance c oss - 640 - pf reverse transfer capacitance c rss - 320 - pf internal source inductance l s measured from the source lead, 6mm (0.25in) from package to center of die modified mosfet symbol showing the internal devic- es inductances - 7.5 - nh internal drain inductance l d measured from the drain- lead, 6mm (0.25in) from package to center of die - 4.5 - nh l s l d g d s hplr3103, HPLU3103
?001 fairchild semiconductor corporation hplr3103, HPLU3103 rev. b thermal resistance junction to case r jc - - 1.4 o c/w thermal resistance junction to ambient r ja - - 110 o c/w (pcb mount steady state) - - 50 o c/w electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units source to drain diode speci?ations parameter symbol test conditions min typ max units continuous source to drain current i sd mosfet symbol showing the integral reverse p-n junction diode - - 52 (note 1) a pulsed source to drain current (note 2) i sdm - - 220 a source to drain diode voltage (note 3) v sd i sd = 28a - - 1.3 v reverse recovery time (note 3) t rr i sd = 34a, di sd /dt = 100a/ s - 81 120 ns reverse recovered charge (note 3) q rr i sd = 34a, di sd /dt = 100a/ s - 210 310 nc notes: 2. repetitive rating; pulse width limited by maximum junction temperature (see figure 11). 3. pulse width 300 s; duty cycle 2%. 4. v dd = 15v, starting t j = 25 o c, l = 300 h, r g = 25 ? , peak i as = 34a, (figure 10). typical performance curves figure 1. output characteristics figure 2. output characteristics d g s 1 100 1000 0.1 1.0 10 100 20 s pulse width t c = 25 o c v gs in decending order v ds , drain to source voltage (v) i d , drain to source current (a) 12v 10v 8.0v 6.0v 4.0v 3.0v 2.5v 15v 10 1 100 1000 0.1 1 10 100 20 s pulse width t c = 150 o c v ds , drain to source voltage (v) i d , drain to source current (a) 12v 10v 8.0v 6.0v 4.0v 3.0v 2.5v 15v v gs in decending order 10 hplr3103, HPLU3103
?001 fairchild semiconductor corporation hplr3103, HPLU3103 rev. b figure 3. transfer characteristics figure 4. normalized drain to source on resistance vs junction temperature figure 5. capacitance vs drain to source voltage figure 6. gate charge waveforms for constant gate current figure 7. source to drain diode forward voltage figure 8. forward bias safe operating area typical performance curves (continued) 1 10 100 1000 24 6 79 v gs , gate to source voltage (v) i d , drain to source current(a) 20 s pulse width v ds = 15v t j = 25 o c t j = 150 o c 3 5 8 0 0.5 1.0 1.5 2.0 2.5 -80 -40 0 40 80 120 160 200 normalized drain to source on resistance t j , junction temperature ( o c) pulse duration = 80 s i d = 46a, v gs = 10v duty cycle = 0.5% max 0 400 800 1200 1600 2000 2400 2800 3200 10 100 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gs c iss c oss c rss c, capacitance (pf) v ds , drain to source voltage (v) 1 v ds = 24v 0 4 8 12 16 20 0 10 20 30 40 q g , total gate charge (nc) v gs , gate to source voltage (v) i d = 34a v ds = 15v 10 100 1000 0.4 1.2 2.0 2.8 t j = 25 o c t j = 175 o c v sd , source to drain voltage (v) i sd , reverse drain current(a) 2.4 1.6 0.8 pulse duration = 80 s i d = 46a, v gs = 10v duty cycle = 0.5% max 1 10 100 1000 1 10 100 limited by r ds(on) area may be operation in this v dss max = 30v v ds , drain to source voltage (v) i d , drain current (a) 10ms 1ms 100 s 10 s hplr3103, HPLU3103
?001 fairchild semiconductor corporation hplr3103, HPLU3103 rev. b figure 9. maximum continuous drain current vs case temperature figure 10. unclamped inductive switching capability figure 11. normalized maximum transient thermal impedance test circuits and waveforms figure 12. unclamped energy test circuit figure 13. unclamped energy waveforms typical performance curves (continued) t c , case temperature ( o c) i d , drain current (a) 0 15 30 45 60 25 50 75 100 125 150 1 10 100 0.001 1000 1 i as , avalanche current (a) t av , time in avalanche (ms) t av = (l)(i as )/(1.3*rated i as v dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] starting t j = 25 o c starting t j = 150 o c 0.1 100 0.01 10 e as point 0.01 0.1 1 2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 t, rectangular pulse duration (s) single pulse z jc , normalized thermal impedance duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 hplr3103, HPLU3103
?001 fairchild semiconductor corporation hplr3103, HPLU3103 rev. b figure 14. gate charge test circuit figure 15. gate charge waveforms figure 16. switching time test circuit figure 17. resistive switching waveforms test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) q g(tot) q gd q gs v ds 0 v gs v dd i g(ref) 0 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 hplr3103, HPLU3103
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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